This relates generally to communications links, and more particularly, to high-speed input-output (I/O) communications links.
A typical communications link includes a transmitter (TX), a receiver (RX), and a channel that connects the transmitter to the receiver. The transmitter transmits a serial data bit stream to the receiver via the channel. Typical high-speed transmit data rates are 1 Gbps (gigabits per second) to 10 Gbps. Communications links operating at such high data rates are often referred to as high-speed serial links or high-speed input-output links.
Ideally, the transmitter outputs the data bits at even intervals using a transmitter clock signal with 50% duty cycle while the receiver latches incoming serial data bits using latching circuits that have been calibrated to remove any undesired offset.
In practice, however, the transmitter clock signal may suffer from duty cycle distortion (i.e., the transmitter clock signal may exhibit a duty cycle that deviates from 50%), which can cause eye openings associated with even and odd data bits being received at the receiver to be different in size (i.e., the eye opening associated with the even data bits may be smaller than the eye opening associated with the odd data bits, or vice versa). Moreover, a first latching circuit that is being used to latch even data bits and a second latching circuit that is being used to latch odd data bits may exhibit non-zero offset even after offset calibration.
The first and second latching circuits sometimes exhibit different residual offset. When data bits exhibiting the smaller eye are being latched using one of the two latching circuits exhibiting poorer offset characteristics, the performance of the communications link will be substantially degraded.